NEW DELHI:
Researchers at the Electrical Engineering Department of the Indian Institute of Technology (IIT) Delhi have developed what the institute describes as the country’s first working, demonstrable micro-Graphics Processing Unit (micro-GPU) designed indigenously, aimed at reducing dependence on imported GPU technology.
Graphics Processing Units (GPUs) are widely used in modern computing hardware, including artificial intelligence and machine learning systems.
“To the best of our knowledge, this is the first working, demonstrable indigenously designed micro-GPU from a university in India,” the researchers said.
According to an official release from IIT Delhi, the project has demonstrated programmable graphics rendering using a custom floating-point GPU engine implemented entirely in Register Transfer Language (RTL) and mapped to a Spartan-7 Field-Programmable Gate Array (FPGA) platform.
The micro-GPU architecture is designed to enable indigenous graphics and display-processing systems for embedded applications.
The hardware architecture is a scalable, programmable graphics processor intellectual property (IP) suitable for applications such as industrial control displays, low-cost human-machine interfaces, e-rickshaw dashboard navigators, inland-water navigation terminals for small fishing boats, educational e-book readers, and other affordable embedded visualisation systems. It can be mapped to application-specific integrated circuits (ASICs) or programmable hardware such as FPGAs.
The institute said the research team is exploring a roadmap towards an 8-16-core, vector-style graphics processor architecture with an optimised compiler and graphics software toolchain. The team also plans to eventually develop a proof of concept using a 65 nm ASIC process node.
The researchers believe that mature semiconductor process nodes such as 65 nm could potentially enable economically viable and practically useful indigenous graphics silicon for embedded-system applications.
The team is seeking funding support for ASIC development, system integration, and eventual commercialisation of the technology.
The project was led by MTech students Nammi Akash and Ravi Teja under the guidance of Professor Jayadeva and Professor Kaushik Saha of the Electrical Engineering Department at IIT Delhi.
In a joint statement, Akash and Ravi Teja said, “Our objective was to create a compact but genuinely programmable graphics-processing architecture suitable for FPGA implementation and future ASIC realisation. We hope such indigenous hardware systems can support affordable digital-access platforms and contribute meaningfully towards bridging the digital divide. We are grateful to our institute, IIT Delhi, for providing the academic environment and the technical platform that enabled this work.”